This invention relates to bit error detection, and more particularly to the detection of a bit error in a system and the isolation of such a bit error within the system. Specifically, the invention concerns the detection of a readout or "soft read error" in a multibit word outputted from a memory in response to a read signal applied thereto combined with the detection of transmission means errors wherein there is provided the capability of distinguishing between readout and transmission errors.
In interrogating or reading most types of memories, including both static and dynamic type memories, there is a possibility of a false output known as a "soft read error" from the memory device. For example, an eight bit binary word may be outputted with a bit error in one of the bit positions. The soft read error is most prevalent in memories where the stored information requires periodic refreshing or is destroyed during a read operation.
In a common dynamic random access memory fabricated as an integrated circuit on a chip substrate, data storage facilities are provided by a plurality of capacitors. Because information is stored as a charge on a small substrate capacitor in the memory device, the level of charge on these capacitors must be sensed in order to output data. In the process of reading or sensing this charge, the charge is removed from the capacitors. The memory device is constructed in order to automatically refresh the memory during a read operation in order that the capacitor may be recharged to retain information.
Two output paths exist for data read from the capacitors in the typical dynamic random access memory. One path is the re-write or refresh path. The second path is the data output path which provides the signal utilized by the memory means user. Because of the possible gain or noise differences existing between the two paths, correct information could be written into the memory during a refresh cycle, while false information is being outputted to the memory device user.
It can therefore be seen that there exists an error mode common to all types of electronic memory devices, but especially prevalent in dynamic type memory devices, that is transient in nature and is also self-correcting. Typical logic systems employing memory means and having error detection means for the aforesaid memory means commonly cause the entire system to cease functioning upon any detection of bit errors including "soft read errors." This situation causes a large number of unnecessary disruptions to the system operation. It can be seen that it would be desirable to have a means of distiguishing between self-correcting soft read errors and hard read errors in order that the memory devices may be more efficiently utilized.
There is a substantial amount of prior art in the area of bit error detection and correction including Chelberg et al U.S. Pat. No. 4,084,236; Nibby Jr. et al U.S. Pat. No. 4,077,565; Carter U.S. Pat. No. 3,949,208; Smith U.S. Pat. No. 3,898,443; Rosenfeld U.S. Pat. No. 3,693,153; Carter et al U.S. Pat. No. 3,688,265; Flinders et al U.S. Pat. No. 3,646,516; Weisbeck U.S. Pat. No. 3,599,146; and Kurtz U.S. Pat. No. 3,568,153.
Although the prior art discloses many means for detecting and correcting bit errors, none of the above noted art relates to the detection of soft read errors and a method of handling soft read errors in an efficient manner.